Three-Dimensional Integrated Circuit (3DIC or 3D-IC) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. Portable devices such as smart-phones and tablet computers are expected to drive adoption of monolithic 3D-ICs. Power and space savings with monolithic 3D-ICs can improve battery life and form factor. Furthermore, heat removal is manageable for these chips despite higher power densities caused by stacking because power consumption for these applications tends to be below 1W.

3DIC is different from 3D packaging of ICs that saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack Multi Chip Module, does not integrate the chips into a single circuit. The chips in the package communicate with off-chip signaling, much as if they were mounted in separate packages on a normal circuit board. In contrast, a 3DIC is a single chip. All components on the layers communicate with on-chip signaling, whether vertically or horizontally. Essentially, a 3DIC bears the same relation to a 3D package that a SoC bears to a circuit board.

3DIC Manufacturing Technologies

  • Monolithic 3DIC Manufacturing Technology – Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. Applications of this method are currently limited because creating normal transistors requires enough heat to destroy any existing wiring. This monolithic 3D-IC technology has been researched at Stanford university under a DARPA sponsored grant.
  • Wafer-on-Wafer 3DIC Manufacturing Technology – Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These “through-silicon vias” (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Wafer-on-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must be the same size – but many exotic materials (e.g. III-Vs) are manufactured on much smaller wafers than CMOS logic or DRAM (typically 300mm), complicating heterogeneous integration.
  • Die-on-Wafer 3DIC Manufacturing Technology – Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dies are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dies may be added to the stacks before dicing.
  • Die-on-Die 3DIC Manufacturing Technology – Electronic components are built on multiple dies, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-on-die is that each component die can be tested first, so that one bad die does not ruin an entire stack. Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).

There are a lot of advantages of 3DIC technology, including: smaller footprint, high-speed operation, low power consumption, low cost, wide bandwidth, and integrated circuit security. There are a few challenges of 3DIC technology, including: risk of higher failure rates, heat buildup in 3DIC, design complexity, etc.