FPGA design challenges is one of the most discussed topics in VLSI design world. Large FPGAs are widely used for ASIC prototyping and as the core of many systems in communications, video/broadcasting and aerospace/defense, to name a few. While the level of integration in today’s FPGAs has enabled their use in a broad range of applications, it has outpaced existing simulation and debugging capabilities. Moore’s law continues to make FPGAs more complex, but it has hit a performance wall when it comes to making the workstations that verify FPGAs run faster. And the “divide and conquer” approach used by simulation farms can’t help much with long serial protocols and video frames that can’t be broken up.

The solution is to off-load the processing of the FPGA design from the simulator to the FPGA itself, thereby accelerating long simulations and enabling complex chip- level and multi-chip FPGA verification and debug that would otherwise not be possible with a typical software-only verification environment.

GateRocket’s RocketDrive accelerates simulation runtimes for large FPGAs by up to 10x or more without a change in methodology, enabling more thorough verification in less time. In addition, GateRocket’s debug environment, RocketVision, helps you cut the number of builds (synthesis + PAR) in half with its unique “soft-patch” capability that lets you make changes to a specific RTL block and run it with the rest of the chip modeled in FPGA hardware. In this way you can try out fixes without rebuilding the FPGA, and find/fix multiple bugs per day.

The GateRocket FPGA Design Verification Debugging software solution has been proven to reduce the verification bottleneck of complex FPGAs by up to 50% or more through an approach that allows designer to bring the accuracy and speed of their FPGA device directly into their native software simulation environment. The result is extremely fast verification throughput, and a highly efficient method to track down and correct design errors. The GateRocket solution has been used effectively for ASIC prototyping with FPGAs as well as in the verification of production programmable logic devices. It has been utilized for specific FPGA challenges in such areas a mil-aero design (thanks to its support of the DO-254 mandate), in the growing area of SERDES design (a demo showing a XAUI core and SERDES elements will be shown at DAC), and DSP implementations in FPGAs (as a result of its integration with tools from MathWorks).