The cost of designing traditional standard cell ASICs is increasing every year. In addition to non-recurring engineering (NRE) and mask costs, development costs are increasing due to design complexity. Issues such as power, signal integrity, clock tree synthesis, and manufacturing defects can add significant risk and time-to-market delays. On the other hand FPGAs offer a viable and competitive option to traditional standard cell ASIC development by reducing the risk of re-spins, high NRE costs, and time-to-market delays.

Programmable logic has progressed from being used as glue logic to today’s FPGAs, where complete system designs can be implemented on a single device. The number of gates and features has increased dramatically to compete with capabilities that have traditionally only been offered through ASIC devices.

Download the ebook (sponsored by Altera) of full design guide to convert from Standard Cell ASIC to FPGA Design: