Design for Testability (DFT) is not limited to chip design such as FPGA, ASIC, or any other IC design. We can Design any system/board for Testability. Design for Test or Testability (DFT), basically an integral part of Design for Manufacturing (DFM), for improving the testability of complex circuits. With higher printed circuit board densities, DFT is now a mandatory requirement for maintaining a competitive profile in today’s marketplace. Implementing DFT in printed circuit board design means providing adequate test coverage while minimizing the number of required test (probe) points, and placing test points to minimize test fixture complexity. Device I/Os have rapidly increased in number and decreased in physical size. Therefore, companies have been compelled to adopt DFT approaches that reduce the need for PCB physical access.

Testability Design Guidelines for FPGA & Processor Board Design

  • Ensure multiple ground pads are distributed across the board to connect oscilloscope ground pins. This should be helpful to do a quality measurement of the signals since closer GNDs can be provided to oscilloscope during signal measurement.
  • VCC and GND testpads should be distinguishable on the board. This is to ensure that the CRO ground is not accidentally connected to VCC pad. Silkscreen markings can be used for distinguishing the VCC and GND pads.
  • In boards which doesn’t have complete power plane distribution for all the voltages, use different voltage pads distributed across the board to verify voltages at different points. In cases where the power planes are broken, there is a chance of voltage drop between source and destination. So it is recommended to measure the voltage at both source and destination.
  • Provide a ground pad near critical signals so that shortest ground can be provided to probe precisely. This would be helpful when doing the signal measurement of high frequency signals to connect the oscilloscope ground very near (~1 cm) to the point of measurement.
  • Provide Logic Analyzer (LA) headers to capture important signals on logic analyser. Group the signals properly before connecting to LA headers.
  • LEDs should be provided on the board to facilitate debugging. LEDs can be used to monitor power supplies, level interrupts, PLD configuration status, reset etc. If multiple status needs to be indicated, use multi color LEDs to save board space.
  • JTAG signals TDI, TCK, TMS should have pullups at the beginning of the chain. TDO should be pulled up at the connector. Signals TDI, TMS and TCK should be pulled up at the entry point to the board. This will ensure that the devices on the JTAG chain do not enter the JTAG state machine, when the boundary scan test is not being performed. For devices using TRST signals, the pullup resistor should be provided as per the vendor recommendations.
  • When devices with different voltages are chained together in a JTAG chain, ensure that the devices can be chained together without damage.