Microtronix®, a leading developer of high-performance intellectual property (IP) cores and FPGA products, introduces a new Camera Link IP Core for supporting all three performance tiers: base, medium and full configurations. The core targets a wide range of industrial and military imaging applications including machine vision, frame grabber and image conversion systems. The Camera Link IP Core offers system integrators a flexible design solution which can be configured to support a wide variety of camera resolutions and data formats. The core is optimized for Altera® Cyclone family of field programmable logic devices and is supplied with an easy-to-use Quartus® SOPC Builder Ready component. The core is supported with a hardware Design Kit and can be implemented in Altera’s Cyclone® FPGAs.

Camera Link Communication Interface IP Core for FPGA System DesignThe Microtronix Camera Link IP Core is designed for building vision systems incorporating Camera Link communication interfaces including Base, Medium & Full Channel Link configurations. The core supports camera control signals, serial communication, and video data. It is designed for building both Camera and Frame Grabber devices.

The Camera Link standard is based on Channel Link® technology developed by National Semiconductor. Channel Link uses LVDS technology for transmitting digital data using a parallel-to-serial transmitter and a serial-to parallel-receiver to transmit data at rates up to 2.38 Gbps. The base Channel Link standard uses 28 bits to represent up to 24 bits of pixel data and 3 bits for Video Sync signals. These consist of Data Valid, Frame Valid, and Line Valid bits. The data is serialized 7:1, and the four data streams and a dedicated clock are driven over five LVDS pairs. The Receiver accepts the four LVDS data streams and one LVDS clock, and then deserializes the data into 28 bits of parallel data and a clock.

The Camera Link IP FPGA core is designed for building both Camera and Frame Grabber devices. It supports camera control signals, bi-directional serial Camera Link communication, and video data. A supporting Quartus® II software configuration GUI streamlines the design process. The use of Altera’s TimeQuest timing analyzer and design constraints achieves timing closure and design fit over temperature, power and voltage to ensure a stable and reliable end product.

The Camera Link IP Core is specifically targeted at industrial video applications including: industrial vision systems, high-speed video interconnects, Camera Link frame grabber devices, interface conversion, and video processing equipment. Features of Camera Link IP Core:

  • Standard Base, Medium & Full Channel Link interfaces
  • Camera and Frame Grabber configurations
  • 7:1 Serializer/Deserializer (SerDes)
  • Supports 8, 10, and 12-bit video resolutions
  • Transmission clock rates to 85 MHz.
  • Bi-directional serial Camera Link communication
  • Configuration GUI streamlines design process
  • Supports Cyclone II, III, and IV FPGA devices
  • Altera SOCP Builder configuration GUI
  • TimeQuest timing analyzer Synopsis Design Constraint file
  • VHDL IP functional simulations models
  • Includes perpetual IP core license with 1 year of updates
  • Altera OpenCore Plus evaluation license available