VLSI FPGA ASIC Design

 

FPGA Controlled Tester for Circuit Board Testing and Debugging

The role of FPGAs is increasing to high-speed and high-end applications. FPGA usage in computer and communications systems has grown in parallel with the number of gates and the hgh-speed capabilities of newer/advanced FPGA devices. Usually FPGA applications are limited by their speed of processing. Now FPGAs are emerging as a likely platform for next-generation […]

Read more >>> FPGA Controlled Tester for Circuit Board Testing and Debugging

Xilinx demonstrated FPGA based Ethernet Audio/Video Bridging (EAVB) network implementation optimized for carrying high-speed data traffic within the automobile. FPGA based Ethernet Audio/Video Bridging (EAVB) network fulfills consumer expectations for higher resolution displays and graphics quality in their driver assistance, navigation and passenger entertainment systems grow, so do the associated challenges of moving content around […]

Read more >>> FPGA-based Ethernet Audio-Video Bridging Network for Cars

Altera’s new Whitepaper “System-Level Debugging and Monitoring of FPGA Designs” describes the latest state-of-the-art methods for debugging and monitoring large FPGA designs both during the simulation phase of development and after device configuration, and details the current practices that Altera has identified across a representative number of customer designs. In addition, the paper presents a […]

Read more >>> System-Level Debugging and Monitoring of FPGA Designs

Timing closure is of critical importance in high-speed FPGA designs. The tools available in Altera’s Quartus II development software are designed to help address the challenges that effect timing closure—the availability of critical resources, the amount of routing congestion both local and global, and the ability to accurately time the logic to avoid timing volitions […]

Read more >>> FPGA Design Optimization Tips for FPGA Timing Closure Issues

August 3, 2011:- Microsemi introduced Intrinsic-ID’s Quiddikey security intellectual property (IP) on its flash-based devices and FPGA development boards including the SmartFusion® customizable system-on-chip (cSoC), as well as ProASIC, IGLOO and Fusion FPGAs. Intrinsic-ID’s security Quiddikey IP includes the company’s patented physical unclonable function (PUF) technology, enabling an added level of security in secure government […]

Read more >>> Intrinsic-ID Security IP for Unclonable FPGA SOC Design

Synopsys Virtual Prototyping Software Tool, Virtualizer addresses the increasing development challenges associated with software-rich semiconductor and electronic products by enabling companies to accelerate both the development and deployment of virtual prototypes. The results? Accelerated time to market, increased designer productivity, and improved product quality. Virtual Prototyping Software Tools are used for prototyping fully custom SOCs, […]

Read more >>> Virtual Prototyping Hardware-Software Tool – Virtualizer

Content Scramble System (CSS) is a Digital Rights Management (DRM) and encryption system employed on almost all commercially produced DVD-Video discs. Content Scrambling System utilizes a proprietary 40-bit stream cipher algorithm. Content Scrambling System has been superseded by newer DRM schemes such as Content Protection for Recordable Media (CPRM) or by Advanced Encryption Standard (AES) […]

Read more >>> Content Scrambling System (CSS) for DVD-Video Piracy Protection

Design for Testability (DFT) is not limited to chip design such as FPGA, ASIC, or any other IC design. We can Design any system/board for Testability. Design for Test or Testability (DFT), basically an integral part of Design for Manufacturing (DFM), for improving the testability of complex circuits. With higher printed circuit board densities, DFT […]

Read more >>> Board Design Testability Guidelines for FPGA & Processor System Design

System design using FPGA, ASIC and microprocessor/microcontroller based system design is significantly different from the regular board design. In this technical article, we will provide you some key recommendations to design FPGA/Processor-based systems successfully. These are suggested by many board design engineers who has good experience in high speed board designs , multi-layered, multi-CPU and […]

Read more >>> Functional Design Guidelines for FPGA & Processor Board Design

Digital System Board should have enough decoupling capacitors. Ideally each VCC pin of a device should have a decoupling capacitor. If the device has VCC pins pretty close to each other (like pins 1,2,3 & 4) then upto 4 VCC pins can be combined and provided with one bigger decoupling capacitor. Also refer to manufacturers […]

Read more >>> Decoupling Capacitors Guidelines for Digital System Board Design

In Digital System Board Design, It is suggested to Tie high or low all the CMOS floating and unused inputs. Leaving inputs floating causes gate puncture (gates goes to intermediate logic creating a low resistance path to the ground thereby damaging the device). It is recommended to tie the TTL unused inputs to logic low […]

Read more >>> Pullup & Pulldown Resistors Guidelines – Digital System Board Design

In Digital System Board Design, It is suggested to Tie high or low all the CMOS floating and unused inputs. Leaving inputs floating causes gate puncture (gates goes to intermediate logic creating a low resistance path to the ground thereby damaging the device). It is recommended to tie the TTL unused inputs to logic low […]

Read more >>> Pull-Up & Pull-Down Resistors Calculations for Floating & Unused Inputs – Digital System Board Design Guide

Microtronix®, a leading developer of high-performance intellectual property (IP) cores and FPGA products, introduces a new Camera Link IP Core for supporting all three performance tiers: base, medium and full configurations. The core targets a wide range of industrial and military imaging applications including machine vision, frame grabber and image conversion systems. The Camera Link […]

Read more >>> Camera Link Communication Interface IP Core for FPGA System Design

Low-Voltage Differential Signaling (LVDS) is a new technology addressing the needs of today’s high performance data transmission applications. The LVDS interface standard is becoming the most popular differential data transmission standard in the industry. This is driven actwo simple features: “Gigabits @ milliwatts!” LVDS interface delivers high data rates while consuming significantly less power than […]

Read more >>> Low-Voltage Differential Signaling (LVDS) Interface

ATPG or Automatic Test Pattern Generation or Automatic Test Pattern Generator, is an electronic design automation method or technology used to find an input or test sequence that, when applied to a digital circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The generated patterns are […]

Read more >>> Automatic Test Pattern Generation (ATPG)

Boundary-Scan Description Language (BSDL) is a mandatory data format for implementing IEEE 1149.1 in a device. BSDL is a subset of VHDL (VHSIC Hardware Description Language) that describes how IEEE 1149.1 is implemented in a device and how it operates. BSDL captures the essential features of any IEEE 1149.1 implementation. BSDL was approved as IEEE […]

Read more >>> JTAG Boundary-Scan: BSDL & HSDL for Hardware Testing

Three-Dimensional Integrated Circuit (3DIC or 3D-IC) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. Portable devices such as smart-phones and tablet computers are expected to drive adoption of monolithic 3D-ICs. Power and space savings with monolithic 3D-ICs can improve battery […]

Read more >>> 3DIC Design & Manufacturing Technologies

Kilopass Technology Inc., a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP), unveiled Itera, the industry’s first and only embedded multi-time programmable (MTP) non-volatile memory in 40nm. Using Itera antifuse non-volatile memory, system-on-chip (SoC) designers can achieve significantly lower costs (70% less), higher performance (24X increase), and improved integration by replacing external […]

Read more >>> Antifuse Non-Volatile Memory is Multi-Time Programmable SOC On-Chip Memory to Replace EEPROM & Flash Memory

KaiSemi Ltd., a fabless semiconductor vendor developed an innovative IP synthesis tool that automatically converts any FPGA netlist directly to ASIC netlist with the push of a button. Based on its unique tool, KaiSemi provides reduced cost ASIC chips, acting as a second-source to any existing FPGA chip, while ensuring identical design functionality dedicated per […]

Read more >>> Automatic FPGA-to-ASIC Conversion Tool & Merging Multiple FPGAs/ASICs/DSP into Single ASIC

FloorDirector is a RFIC physical design backend designer tool for chip-level noise reduction of EMI/EMC and wireless RF-noise during wireless IC design. By optimizing the digital design in the implementation phase before physical implementation, backend designers using FloorDirector are now able to reduce IC-level noise, Electromagnetic Interference (EMI) and IR Drop, thereby reducing development time […]

Read more >>> EMI/EMC & RF-Noise Reduction in Wireless RF IC Physical Design

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