VLSI FPGA ASIC Design

 

C to FPGA Converter for Image Processing DSP & Encryption Algorithms

Impulse C-to-FPGA compiler supports Pico Computing M-Series FPGA modules that used Xilinx Virtex-6 FPGAs. Using Impulse C™-to-FPGA compiler, DSP algorithms can be optimized for lower power, higher parallel-streaming operation on an FPGA, These modules currently for security and bioinformatics. The Impulse tools further enhance these solutions by enabling users to mix VHDL and Verilog with ANSI C.

Read more >>> C to FPGA Converter for Image Processing DSP & Encryption Algorithms

Intel announced the configurable Intel® Atom™ processor E600C series, which features an Intel® Atom™ E600 processor (formerly codenamed “Tunnel Creek”) paired with an Altera Field Programmable Gate Array (FPGA) in a single package. The new Intel Atom processor provides greater flexibility and faster time-to-market for customers, who can now more readily handle design changes without […]

Read more >>> FPGA ReConfigurable Intel Atom Processor System-on-Chip (SoC)

Microtronix, a leading supplier of performance memory controller intellectual property (IP) cores today announced it has been selected by Arrow and Altera as the preferred memory controller IP Core partner for the new BeMicro software development kit (SDK). As a long term and committed Altera AMPP design partner, Microtronix has enhanced their Multi-port SDRAM Memory […]

Read more >>> FPGA Mobile DDR Memory Controller IP Core Development

Microsemi Fusion mixed signal FPGAs are now available with 100% temperature screening from -55 degrees C to +100 degrees C. This advancement enables the company to bring the unique mixed signal integration advantages of Fusion to the military, avionics, and defense industries, where highly reliable operation at extreme temperatures is needed. Designers can take advantage of the inherent reprogrammability, high reliability and nonvolatility of the Fusion devices, which offer the additional benefit of firm error immunity. In addition, by offering analog and digital integration in a single chip, Fusion mixed signal FPGAs significantly reduce board space.

Read more >>> Mixed Signal FPGA – Fusion FPGA

Microchip Technology Inc. today announced its first stand-alone I2C™ Real-Time Clock/Calendar (RTCC) family. All six MCP794XX devices are highly integrated at a low cost, including ample amounts of on-chip EEPROM and SRAM, as well as a user-lockable section of EEPROM available for a 64-bit reprogrammable unique ID that can be factory-programmed with a MAC address. […]

Read more >>> Real-Time Clock & Calendar (RTCC) Microchip

Actel Corp. announced its ProASICPLUS and ProASIC®3 FPGAs have been selected by Advantech, Co., Ltd. for use in its networking and gaming platforms. Based in Taiwan, Advantech provides solutions in the e-world computing and web-based automation fields through its trusted ePlatform services. Advantech took full advantage of the inherent capabilities of the flash technology, specifically […]

Read more >>> ProASIC FPGAs for Networking and Gaming Platforms

SuperSpeed USB 3.0 Features, Specifications and comparison with HiSpeed USB 2.0.

Read more >>> SuperSpeed USB 3.0 Specifications and Comparison with HiSpeed USB 2.0

Q. Why is it important to keep code for generators/scoreboards and code for BFMs separated? Q. Which of the parts in the testbench should add data to the scoreboard? Q. What is the Verification testing? Q. What is the difference between verification and validation? And what are procedures of doing the same? Q. What is […]

Read more >>> FPGA & ASIC Verification & Validation Questions

Q. Explain the flow of physical design and inputs and outputs for each step in flow. Q. Why higher metal layers are preferred for Vdd and Vss? Q. Why clock is not synthesized in DC? Q. Which layer is used for clock routing and why? Q. Which is more complicated when you have a 32 […]

Read more >>> ASIC Backend Physical Design Questions

The cost of designing traditional standard cell ASICs is increasing every year. In addition to non-recurring engineering (NRE) and mask costs, development costs are increasing due to design complexity. Issues such as power, signal integrity, clock tree synthesis, and manufacturing defects can add significant risk and time-to-market delays. On the other hand FPGAs offer a […]

Read more >>> Standard Cell ASIC to FPGA Conversion Design Guide

Few important characteristics and features of pipeline concept: – Processes more than one instruction at a time, and doesn’t wait for one instruction to complete before starting the next. Fetch, decode, execute, and write stages are executed in parallel – As soon as one stage completes, it passes on the result to the next stage […]

Read more >>> Pipelining of Microcontroller Microprocessor

Moore State Machine Moore machines are the simpler of the two standard types. The output is a function only of the current state of the machine. Mealy State Machine The outputs of Mealy machines are a function of the current state of the machine plus the inputs. This additional path provides more flexibility, but may […]

Read more >>> Finite State Machine (FSM) Encoding Styles and Improvement Tips

A state machine is a digital device that traverses through a predetermined sequence of states in an orderly fashion. A state is a set of values measured at different parts of the circuit. A simple state machine can consist of PAL device based combinatorial logic, output registers, and buried (state) registers. The state in such […]

Read more >>> Mealy and Moore Finite State Machines (FSM)

Often VLSI engineers need to draw timing diagrams during the documentation at various design stages. It is possible that your VHDL or Verilog HDL code can be used to generate timing diagrams quickly. In some cases, the timing diagrams can be generated by the design tool itself based on HDL or any other code executed […]

Read more >>> VHDL/Verilog Code Timing Diagram Generation Software Tools

Often digital electronics engineers have to draw timing diagrams during the documentation at various design stages. In some cases, the timing diagrams can be generated by the design tool itself based on HDL or any other code executed by the tool. It may not be the case if the engineer wants to draw timing diagrams […]

Read more >>> Timing Diagram Creation/Generator Software Tools

FPGA to ASIC Design Converter Software Tools. FPGA Design For Portability. FPGA to ASIC Migration Design Practices. FPGA to ASIC SOC IP Conversion. FPGA-ASIC Physical Design Implementation. ASIC to FPGA Conversion.

Read more >>> FPGA to ASIC Conversion – FPGA-ASIC Design Migration

FPGA Design For Portability for FPGA to ASIC SOC Conversion. FPGA – ASIC Potential voltage change. FPGA-ASIC JTAG implementation. FPGA-ASIC system timing requirements vs. FPGA timing capability. Develop robust design verification suites. Follow industry RTL coding standards.

Read more >>> FPGA Design For Portability – FPGA to ASIC Conversion

VHDL to Verilog Code Converter, Verilog to VHDL Code converter, VHDL Code Converter Tools, Verilog Code Translator Tools. VHDL-Verilog Code Conversion Software Tools. Tips on Code Conversion Between VHDL and Verilog.

Read more >>> VHDL to Verilog to VHDL Code Converter Tools & Tips

Medical imaging equipment is taking on an increasingly critical role in healthcare as the industry strives to lower patient costs and achieve earlier disease prediction using noninvasive means. To provide the functionality needed to meet these industry goals, equipment developers are turning to programmable logic devices such as Altera’s FPGAs. Earlier prediction and treatment are […]

Read more >>> FPGA Design – Medical Imaging System Implementation –

The FPGA’s inherent flexibility has proven indispensable for the creation of external I/O interfaces. However, unless I/O is implemented on a daughter card (mezzanine module), replacing the physical I/O components and connectors requires changing the FPGA board design. To avoid these costs, designers have historically relied on the PCI Mezzanine Card (PMC) and Switched Mezzanine […]

Read more >>> FPGA Mezzanine Card (FMC) I/O Design Flexibility

Showing results 41 - 60 of 75 for the category: VLSI FPGA ASIC Design.