May 3, 2011:- BittWare announced today, at the Embedded Systems Conference, the Anemone floating point co-processor chip for use with Altera’s high performance FPGAs. Anemone represents a new hybrid approach for complex floating point signal processing that adds a low-power, C-programmable computer engine to world-class FPGA technology from Altera. Because it was specifically architected to be used alongside an FPGA as a co-processor, the Anemone simultaneously achieves superior power efficiency and processing performance. This joint C-language and RTL (VHDL, Verilog) solution of Anemone plus Altera FPGAs provides users with the unique ability to partition algorithms into hardware or software, enabling them to design a thoroughly optimized system solution with superior development productivity and unmatched system size, weight, and power.

Each Anemone features 16 processors, providing 32 GFLOPS of floating point processing while consuming only 2 Watts of total chip power. Multiple Anemones can be gluelessly connected, thereby scaling to create compute blocks of up to 4096 processors providing 8 TFLOPs of floating point performance. Delivering a standard processor software development environment that tightly integrates with a world-class FPGA platform from Altera, the Anemone allows the best of two worlds to be combined – facilitating increased productivity and optimal solutions for complex signal processing applications.

As most of the DSP design engineers do not have knowledge on HDL programming for FPGA based SOC development, they prefer to work with floating-point DSP processor using C-language programming. Later, with the use of C-language to FPGA programming tools, the VLSI SOC IP development is possible. But it is not an optimized solution. By using Anemone FPGA floating-pint co-processor chip, Now it is easy to execute FPGA based DSP projects, with combination of DSP algorithms development using C-language and VHDL/Verilog combination. Also, it is easy to design projects for multimedia SOC systems that need both DSP and FPGA features.