Here is the list of FPGA based ARM Microprocessor and Microcontroller projects ideas for experimenting with VHDL and Verilog HDL, for final year projects of electronics engineering students. Below list has VHDL/Verilog FPGA based projects for wide applications of Microprocessor/Microcontroller based systems.

  • FPGA Design of AMBA AHB to PVCI Bridge using FPGA with Verilog/VHDL code
  • FPGA Design of AHB Master/Slave using FPGA with Verilog/VHDL code
  • FPGA Design of Asynchronous FIFO using FPGA with Verilog/VHDL code
  • FPGA Design of 16/32/64-bit Low Power RISC/CISC Processor using FPGA with Verilog/VHDL code
  • VLSI Implementation of Address Generation Coprocessor
  • FPGA Design of Cell phone Controller using VHDL/Verilog HDL
  • FPGA Design of Bus Arbiter using VHDL/Verilog HDL
  • FPGA Design of Basic RSA Encryption Engine
  • FPGA Design of Basic DES Crypto Core
  • FPGA Design of Associate Memory using VHDL/Verilog HDL
  • VLSI Design and Implementation of Arithmetic Logic Unit using VHDL/Verilog HDL
  • FPGA Design of SDRAM Memory Controller Core
  • FPGA Design of FlashMemory Controller Core
  • FPGA Design of PVCI Master/Slave using FPGA with Verilog/VHDL code
  • FPGA Design of Wishbone Controller using FPGA with Verilog/VHDL code
  • FPGA Design of Booth Multiplier using FPGA with Verilog/VHDL code
  • The Arise Approach for Extending Embedded Processors with Arbitrary Hardware Accelerators
  • Low Power Design of Precomputation-Based Content-Addressable Memory
  • VLSI Design and Implementation of DMA using VHDL/Verilog HDL
  • VLSI Design and Implementation of Data Routing Multiplexer using VHDL/Verilog HDL
  • Implementation of a Multi-Channel UART Controller based on FIFO Technique and FPGA
  • Implementation of a Multi-Coder Processor for the WTLS with High Compression Ratio
  • Custom Floating-Point Unit Generation for Embedded Systems
  • Cost-Efficient SHA Hardware Accelerators
  • Low-Power Low-Area Multiplier Based on Shift-and- Add Architecture
  • Block-Based Multi-period Dynamic Memory Design for Low Data-Retention Power
  • Area-Efficient Arithmetic Expression Evaluation using Deeply Pipelined Floating Point Cores Using VHDL/Verilog HDL
  • An improved RC6 algorithm with the same structure of encryption and decryption
  • Robust UART Architecture based on Recursive Running Sum
  • Novel Multiplexer Based Truncated Array Multiplier
  • Low-Power Multiplier with the Spurious Power Suppression Technique
  • Full-Adder-Based Methodology for the Design of Scaling Operation In Residue Number System
  • Framework for Correction of Multi-Bit Soft Errors in L2 Caches based on Redundancy
  • Simulation of IEEE 802.11a and b physical layer
  • Designing of I2C Master Core / SPI Master Core using Verilog HDL
  • Compact AES Encryption Core for FPGA
  • Design and Synthesis of Programmable Logic Block with Mixed LUT and Macrogate
  • FPGA Design of Risc Controller using Verilog HDL
  • FPGA Design of Universal Sync / Async Receiver and Transmitter (USART)
  • High-Speed VLSI Architecture for Reed-Solomon Decoder
  • Design and Synthesis of Programmable Logic Block with Mixed LUT and Macrogate
  • FPGA Design and Implementation of Elevator Controller