Timing closure is of critical importance in high-speed FPGA designs. The tools available in Altera’s Quartus II development software are designed to help address the challenges that effect timing closure—the availability of critical resources, the amount of routing congestion both local and global, and the ability to accurately time the logic to avoid timing volitions that could otherwise be caused by skews within the clock network—but often simple HDL changes will go a long way towards resolving timing issues and reducing the time it takes to achieve timing closure.

Today’s larger FPGAs are quickly approaching 1M LEs, which can make timing closure a difficult process in extremely large designs. Good coding practices such as retiming logic, pipelining where practical, and avoiding high fan-out nodes can make the problem much easier. In addition, partitioning the design and good clock management at the start will go a long ways towards avoiding issues once the design is complete. However, these suggestions are not all inclusive and may not solve all timing issues, Altera has developed advanced tools and has highly trained support personnel who are ready and committed to help the user close timing in their designs.

Altera released a whitepaper, “Tips and Techniques for 28-nm Design Optimization”, focuses on the challenges that affect timing closure and discusses how simple HDL changes can help resolve timing issues and reduce the time needed to achieve timing closure. This white paper addresses these possible HDL changes and their relationship to the architecture and layout of the FPGA. This paper is not intended to be a comprehensive look at all timing issues but a guideline to good coding practices with a specific emphasize on how these apply to designs implemented in Altera’s 28-nm portfolio of devices.

Altera Whitepaper Download Link: http://www.altera.com/literature/wp/wp-01172-design-optimization.pdf