Semiconductor intellectual property (IP) provider CAST, Inc. has expanded its suite of video and image compression IP with a new H.264 Main Profile Video Encoder core. This H.264-MP-E FPGA IP core implements a video encoder compatible to the Main profile of the H.264 standard, also known as MPEG-4 Part 10.

The H.264-MP-E core can encode at Full HD (1080p@30) or higher rates, even in low-cost FPGAs. Employing innovative techniques and algorithms, it provides quality beyond typical H264 hardware Main Profile encoders. The core can perform constant bit rate (CBR) compression that produces the highest possible quality while fitting the output to a specified bit rate, or constant-Qp, variable bit rate (VBR) compression to achieve a uniform quality level among frames.

FPGA/ASIC H.264/AVC HD&ED Video Encoder IP Core

FPGA/ASIC H.264/AVC HD&ED Video Encoder IP Core


The H.264-MP-E FPGA core can be configured to operate on Intra-Only mode, offering compression efficiency superior than this of JPEG and competitive to this of JPEG2000. Under this configuration the requirements for an external memory can be eliminated, the core’s size is cut to half, and the output stream remains H264 compliant. With Intra-only compression each frame is coded independently, allowing for smaller processing delays, easier video editing, and enhanced error resilience.

The core is designed for ease and trouble-free integration into FPGA based video system. It can automatically convert incoming frames to the macroblock format required by the H.264 standard, and it outputs the standard H.264 Annex B NAL byte stream. Also, the employed CBR algorithm provides user-controlled granularity, and the CBR output stream is HRD compliant respecting decoder’s buffering requirements. Furthermore, this FPGA core operates independently from a host processor and is run-time programmable for user control over compression parameters and bit rate options. Finally, a flexible external memory interface makes the core independent of memory type—supporting SRAM, SDRAM, or DDRAM—and more tolerant to the large delays and latencies typically present on a shared bus architecture.

The core is designed for reuse and reliability, and has been rigorously verified and FPGA proven. System integration is facilitated by the core’s complete verification environment, with additional aids for system-on-chip simulation available such as a software bit-accurate model (BAM) and a complete hardware/software reference design system.

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:

  • HDL RTL source code (ASICs) or post-synthesis netlist (FPGAs)
  • Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
  • Software (C++) Bit-Accurate Model and test vector generator
  • Synthesis scripts (ASIC) or place and route script (FPGAs)
  • Simulation script, vectors and expected results
  • Comprehensive user documentation, including detailed specifications and a system integration guide