Q. What is the full form of RTL?
Q. What is the difference between RTL and HDL?
Q. Draw the state diagram to detect a sequence?
Q. Draw the state diagram of a traffic light controller?
Q. Which one is faster Carry look ahead or ripple carry adder?
Q. What is the difference between Big Endean format and Little Endean format?
Q. Can you model SRAM at RTL level?
Q. What do you mean by concurrent statement?
Q. Define component instantiation?

Q. What is the difference between variable and signal?
Q. List some sequential statements?
Q. Define a test bench?
Q. What are the advantages of test benches?
Q. What is the difference between behavioral simulation and timing simulation?
Q. Does frequency of operation depend on critical path in a circuit? Justify?
Q. What is slack?
Q. What are different types of scaling? Which one is used and why?
Q. What are the different design styles in VLSI?
Q. What is the full form of ABEL?
Q. What is entry delay and exit delay?
Q. What is Controllability and Observability in testing?
Q. What is fault coverage?
Q. What is DFT? What is its importance?
Q. Expand BIST? Explain?
Q. What is the difference between testing and verification?
Q. Given a circuit with a fault you have to find the test vector to detect that fault?
Q. Consider a counter. I want it to sense odd pulses or even pulses (alternate pulses).How will you do it?
Q. What is Synthesis?
Q. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
Q. What’s the critical path in a SRAM?
Q. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
Q. Draw a 6-T SRAM Cell and explain the Read and Write operations
Q. Draw the SRAM Write Circuitry
Q. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
Q. How will you allocate your time between architecture, coding, and verification?
Q. How do you differentiate between coding in C/C++ and at RTL (Register Transfer Level) ?
Q. How to implement Half-adder and full-adder in RTL?
Q. When the latches are inferred in RTL ?