Altera’s new Whitepaper “System-Level Debugging and Monitoring of FPGA Designs” describes the latest state-of-the-art methods for debugging and monitoring large FPGA designs both during the simulation phase of development and after device configuration, and details the current practices that Altera has identified across a representative number of customer designs. In addition, the paper presents a platform that enables FPGA designers to easily add runtime visibility into their FPGA systems while ensuring the scalability needed in today’s increasingly large designs and compilation times.

today’s FPGA designs can be divided into two different categories: those with embedded soft-core processors and those without. This division is useful when examining what debugging and monitoring infrastructure designers use in their FPGA systems. The techniques discussed in this paper are used both to collect data needed for root-cause diagnosis of defects and to monitor the performance of a system under a real-world load.

This white paper explored the current state-of-the-art methods for debugging and monitoring large FPGA systems and presented a set of requirements needed to be met by the infrastructure tasked to provide system visibility. To meet these requirements, Altera created System Console, a platform that provides users with the flexibility, reusability, and efficiency required to solve today’s wide range of system debugging needs.

Altera Whitepaper Download Link: