Printed circuit board (PCB) layout design becomes more complex for high-speed system design with high frequency and higher device pin density. A successful high-speed board must effectively integrate the devices and other elements while avoiding signal transmission problems associated with high-speed I/O standards. Because today’s high density CMOS devices feature fast I/O pins, a wide variety of high-speed features, and edge rates less than a hundred picoseconds, it is imperative that an effective design successfully: Reduces system noise by filtering and evenly distributing power to all devices, Terminates the signal line to diminish signal reflection, Minimizes crosstalk between parallel traces, Reduces the effects of ground bounce, and Matches impedance.

Here are the general layout guidelines for printed circuit boards (PCB), which exist in relatively obscure documents, are summarized. Some guidelines apply specifically to microcontrollers; however, the guidelines are intended to be general, and apply to virtually all modern CMOS integrated circuits.

Crosstalk Reduction Guidelines for Microstrip or Stripline PCB Layouts

  • Widen spacing between signal lines as much as routing restrictions will allow. Try not to bring traces closer than three times the dielectric height.
  • Design the transmission line so that the conductor is as close to the ground plane as possible. This technique will couple the transmission line tightly to the ground plane and help decouple it from adjacent signals.
  • Use differential routing techniques where possible, especially for critical nets (i.e., match the lengths as well as the gyrations that each trace goes through).
  • If there is significant coupling, route single-ended signals on different layers orthogonal to each other.
  • Minimize parallel run lengths between single-ended signals. Route with short parallel sections and minimize long, coupled sections between nets.

High-Speed PCB Layout Design Guidelines for Signal Integrity Improvement

  • Keep clock traces as straight as possible. Use arc-shaped traces instead of right-angle bends.
  • Do not use multiple signal layers for clock signals.
  • Do not use vias in clock transmission lines. Vias can cause impedance change and reflection.
  • Place a ground plane next to the outer layer to minimize noise. If you use an inner layer to route the clock trace, sandwich the layer between reference planes.
  • Terminate clock signals to minimize reflection.
  • Use point-to-point clock traces as much as possible.

PCB Layout Design Guidelines for EMI Inrference Noise Reduction

Electromagnetic interference (EMI) is directly proportional to the change in current or voltage with respect to time. EMI is also directly proportional to the series inductance of the circuit. Every PCB generates EMI. Precautions such as minimizing crosstalk, proper grounding, and proper layer stack-up can significantly reduce EMI problems. Component selection and proper placement on the board is very important to controlling EMI. The following guidelines can help reduce EMI:

  • Select low-inductance components, such as surface mount capacitors with low ESR, and effective series inductance (ESL).
  • Use proper grounding for the shortest current return path.
  • Use solid ground planes next to power planes.
  • In unavoidable circumstances, use respective ground planes next to each segmented power plane for analog and digital circuits.