Semiconductor design is starting to see the adoption of 3-D IC packages. These packages involve stacking multiple bare die vertically using connections that go directly though the silicon. Through-silicon vias (TSV) result in shorter and thinner connections that can be distributed across the die. This reduces package size and power consumption while increasing performance due to the improved physical characteristics of the very small TSV connections compared to the much larger bond wires used in traditional packaging. But TSVs complicate the test process and 3-D ICs require new approaches to solve this problem.

A challenge is how to test the TSV connections between the stacked memory and logic die. There is generally no external access to TSVs, making the use of automatic test equipment difficult at best. Functional test approaches (for example, where an embedded processor is used to apply functional patterns to the memory bus) are possible but are slow, lack test coverage, and offer little to no diagnostics. Therefore, ensuring that 3D ICs can be economically produced calls for new test approaches.

Built-in Self-Test (BIST) for 3-D Chips

One of the possible approaches to the test and diagnostics challenges of stacked memory ICs on logic TSV connections builds upon built-in self-test (BIST) techniques that are used to test embedded IC functional blocks within system-on-chip (SoC) devices. In this approach to 3D test, a BIST engine is integrated into the logic die and communicates to the TSV-based memory bus that connects the logic die to the memory. For this approach to work, two different techniques to existing embedded memory BIST approaches are necessary.

BIST is fully run-time programmable. Using only the standard IEEE 1149.1 JTAG test interface, the BIST engine can be programmed in silicon to adapt to different memory counts, types and sizes stacked on top of the logic die. Because the BIST engine is embedded into the logic die and can’t be physically modified without a design re-spin, this adaptability becomes essential.

Focused-Ion Beams Analyze Deep Failures on ICs and MEMS

In 3-D packaging integration, stacking wafers and dies of mixed, heterogeneous technologies is fraught with difficulties. Wire-bond and TSV (through-silicon via) connections between wafers must be highly reliable, yet ultra-thin ICs and MEMS (microelectromechanical systems)-based sensors are fragile and can be easily damaged.

For analyzing 3-D stacked ICs, Fraun­hofer EMFT (Research Institution for Modular Solid State Technologies) Device and 3D Integration department have used a conventional FIB (focused ion beam) system with a low milling rate for sample preparation, and then a SEM (scanning electron microscope) for structural and failure analysis. The cross section produced by the FIB enables you to see the TSV structures with very good resolution.