Low-Voltage Differential Signaling (LVDS) is a high-speed, low-voltage, low-power, and low-noise general-purpose I/O interface standard. The low-voltage swing and differential current mode outputs significantly reduce electromagnetic interference (EMI). These outputs have fast edge rates that cause signal paths to act as transmission lines. Therefore, ultra-high-speed board design and differential signal theory knowledge is especially useful for designing a board containing high-end microprocessors, DSPs, ASIC SOCs and FPGAs that integrate LVDS. In addition, a number of factors, such as differential traces, impedance matching, crosstalk, and EMI, have to be considered while designing an LVDS board.

As a technology, LVDS is relevant in systems where the data rates range from around 100 MHz to 2 GHz. At these frequencies a PCB can no longer be treated as a simple collection of interconnects. Traces carrying these high-speed signals need to be treated like transmission lines. These transmission lines should be designed with appropriate impedance and they need to be correctly terminated.

PCB Design & Layout Guidelines for LVDS Boards

  • To ensure minimal reflections and maintain the receiver’s common mode noise rejection, run the differential traces as closely as possible after they leave the driving IC. Also, to avoid discontinuities in the differential impedance, the distance between the differential LVDS signals should remain constant over the entire length of the traces.
  • To minimize skew, the electrical lengths between the differential LVDS traces should be the same. Arrival of one of the signals before the other creates a phase difference between the signal pair, which impairs the system performance by reducing the available receiver skew margin (RSKM).
  • Minimize the number of vias or other discontinuities on the signal path.
  • Any parasitic loading, such as capacitance, must be present in equal amounts to each line of the differential pair.
  • To avoid signal discontinuities, arcs or 45 degree traces are recommended instead of 90 degree turns.
  • Traces for LVDS signals should be closely coupled and designed for 100W differential impedance.
  • Due to the high speed of LVDS, impedance matching is very important, even for very short runs. Any discontinuities in the differential LVDS traces will cause signal reflections, thereby degrading the signal quality. These discontinuities also increase the common mode noise and will be radiated as EMI. The LVDS outputs, being current mode outputs, need a termination resistor to close the loop and will not work without the resistor termination. The value of this termination resistor (RT) is chosen to match the differential impedance of the transmission line and can range from 90 ohms to 110 ohms (typically 100 ohms).
  • To reduce crosstalk between LVDS and single-ended signals such as LVTTL, SSTL-3, SSTL-2, and similar standards, the differential LVDS signals must be isolated from single-ended signals. If the LVDS and single-ended signals are not placed sufficiently apart from one another, the single-ended signals may cause some interference on the differential pair.
  • Isolate LVDS signals from TTL signals to reduce crosstalk (preferably on different layers).
  • Separate LVDS ground and supply planes.
  • Keep stub lengths as short as possible.
  • Multiple vias should be used to connect to power and ground planes.
  • Keep the LVDS drivers and the receiver as close to any connectors as possible.
  • The physical length of each trace between the transmitter outputs and the connector should be matched to within 5 mm of each other to reduce data skew.
  • Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals. Dedicating planes for VCC and ground are typically required for high-speed design.
  • Bypass each LVDS device and also use distributed bulk capacitance. Surface mount capacitors placed close to power and ground pins work best.
  • Keep drivers and receivers as close to the (LVDS port side) connectors as possible. This helps to ensure that noise from the board is not picked up onto the differential lines and will not escape the board as EMI, from the cable interconnect.
  • Keep ground PCB return paths short and wide. Provide a return path that creates the smallest loop for the image currents to return.