Two common noise-related analog phenomena encountered by FPGA digital designs are ground bounce and VCC sag. Ground bounce and VCC sag exist to some degree in almost every board. Normally, if ground bounce occurs on a board, VCC sag occurs as well. Ground bounce occurs when most, if not all, of the bits of the data bus simultaneously switch from 1 to 0. During ground bounce, the device ground rises, or bounces, relative to the board ground.

Many printed circuit boards (PCBs) have data buses running between devices with the bits of the bus placed adjacently to make debugging and routing the signals on the board easier. While this makes board and device design simpler, it can create some problems with signal integrity, including ground bounce and VCC sag.

Due to the inductance, a voltage is produced between the device ground and the board ground, which is proportional to the rate of change in current, or V = L × (di/dt). VCC sag occurs in the same manner as ground bounce, but it is more prevalent when the I/O pins switch from 0 to 1 and affects the internal VCC of the device instead of the GND. Design methods that reduce the inductance and reduce the rate of change of current decrease the amount of ground bounce and VCC sag. The following are the guidelines to reduce ground bounce and VCC sag:

  • Configure unused I/O pins as output pins, and drive the output low to reduce ground bounce. This configuration will act as a virtual ground.
  • Configure the unused I/O pins as output, and drive high to prevent VCC sag.
  • Create a programmable ground or VCC next to switching pins.
  • Reduce the number of outputs that can switch simultaneously and distribute them evenly throughout the device.
  • Manually assign ground pins in between I/O pins. (Separating I/O pins with ground pins prevents ground bounce.)
  • Turn on the slow slew rate logic option when speed is not critical.
  • Eliminate sockets whenever possible.
  • Depending on the problem, move switching outputs close to either a package ground or VCC pin. Eliminate pull-up resistors, or use pull-down resistors.
  • Use multi-layer PCBs that provide separate VCC and ground planes to utilize the intrinsic capacitance of GND-VCC plane.
  • Create synchronous designs that are not affected by momentarily switching pins.
  • Add the recommended decoupling capacitors to VCC/GND pairs.
  • Place the decoupling capacitors as close as possible to the power and ground pins of the device.
  • Connect the capacitor pad to the power and ground plane with larger vias to minimize the inductance in decoupling capacitors and allow for maximum current flow.
  • Use wide, short traces between the vias and capacitor pads, or place the via adjacent to the capacitor pad.
  • Traces stretching from power pins to a power plane (or island, or a decoupling capacitor) should be as wide and as short as possible. This reduces series inductance, and therefore, reduces transient voltage drops from the power plane to the power pin. Thus, reducing the possibility of ground bounce.
  • Use surface-mount low effective series resistance (ESR) capacitors to minimize the lead inductance. The capacitors should have an ESR value as small as possible.
  • Connect each ground pin or via to the ground plane individually. A daisy chain connection to the ground pins shares the ground path, which increases the return current loop and thus inductance.

Reference: Altera Whitepaper on Ground Bounce & Vcc Sag Reduction.