Nexus Technology, Inc. has today introduced Serial RapidIO Gen2 analysis tools for next generation serial buses. This product will be used in conjunction with a Tektronix logic analyzer to enable non-intrusive monitoring and analysis of target systems from the physical coding sublayer to full-duplex link protocol, as well as a generator for stimulus injection at all speeds of Serial RapidIO up to 6.25Gbps.

This product enables passive monitoring, debugging, and target system analysis of all speeds of Serial RapidIO Gen2 and Gen1 from the physical coding-sublayer (PCS), through serial protocol, to full-duplex link protocol exchanges. Stimulus transmitters allow for injection of SRIO packets, control symbols, and 8b/10b characters.

Srial Bus Analyzer
Acquisition of Serial RapidIO x4/x2/x1, full-duplex mode links is available for all speeds of Serial RapidIO up to 6.25-Gbps. The Serial RapidIO data is automatically descrambled, decoded and aligned, for easy debug and analysis. Real-time error checking capabilities allow the user to quickly root-cause system level failures.

Real time filtering can be used to filter out IDLE sequences and other types of data to more efficiently capture and store the packet and control symbol data. This allows the user to capture an event of interest as well as the conditions that resulted in the occurrence of that event on the Serial RapidIO bus.

This product also supports transmission of stimulus data, including SRIO packets, control symbols and 8b/10b characters in x4/x2/x1 mode. These transmitters allow testing of Serial RapidIO receivers on a user system for different link conditions and error recovery logic. The transmitters can also be used as a substitute for the Serial RapidIO transmitter on the user system to quickly recreate infrequent events and test the system response. Stimulus data can be injected into a continuous IDLE sequence or the stimulus can loop on a predefined data pattern. 64k-Symbols of stimulus memory is available.

Protocol Analysis Features

  • Embedded clock recovery
  • x4, x2, or x1 lane widths supported
  • Data rates of 6.25-, 5.00-, 3.125-, 2.50-, and 1.25Gbps
  • Physical Coding Sub Layer features supported
    • 8b/10b decoding
    • Flexible synchronization state machine
    • Flexible alignment state machine
    • Marking of invalid code groups
    • Automatic descrambling of packet and control symbol data as required
  • All packets and packet fields from LP-Serial physical layer, PCS, and PMA layers available for analysis
  • Long and short control symbol formats supported
  • Real-time CRC checking for packets and long/short control symbols (CRC-16, CRC-13, & CRC-5)
  • Visibility and storage of the acquired and analyzed data is provided through a Tektronix logic analyzer

Real Time Analysis Features

This product supports the real time monitoring and triggering of full-duplex links for the following conditions.

  • Packets
  • Control Symbols
  • Idle Sequences
  • CRC Errors
  • Disparity Errors
  • Lanes Locked to Data
  • Lanes Synchonized
  • Lanes Aligned
  • Invalid Character in Symbol or Packet
  • Packet Header
  • /SC/ or /PD/ Control Symbols
  • Start-Of-Packet, Packet-Cancel, & End-Of-Packet Controls