Silicon Labs introduces portfolio for 56G/112G SerDes clocking

Silicon Labs has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM-4 SerDes and emerging 112G serial applications.

Silicon Labs is now able to offer a comprehensive selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and XOs for 100/200/400/600G designs that satisfy sub-100 fs reference clock jitter requirements with margin.

As more manufacturers migrate to 56G PAM-4 SerDes technology to support higher bandwidth 100G+ Ethernet and optical networking designs, in order to meet stringent requirements of 56G SerDes reference clocks, hardware developers often require clocks with sub-100 fs (typical) RMS phase jitter specifications. These designs typically use a mix of other frequencies for CPU and system clocks.

Silicon Labs is now the first timing supplier to be able to provide fully integrated clock IC solutions for 56G designs that integrate SerDes, CPU and system clocks into a single device.

In 56G applications, hardware developers often seek complete clock tree solutions guaranteeing sub-100 fs RMS phase jitter to ensure sufficient margin and de-risk product development. Silicon Labs’ new clock and oscillator products meet these 56G SerDes requirements today, as well as the needs of emerging 112G serial SerDes designs that will ramp in data centre and communications applications in the future.

Silicon Labs’ Si5391, any-frequency clock generator, is the only clock generator currently on the market that can provide all clock frequencies needed in 200/400/600G designs from a single IC while delivering sub-100 fs RMS phase jitter performance for 56G SerDes reference clocks.

Featuring up to 12 differential outputs, the Si5391 clock is available in frequency flexible A/B/C/D grade options. A Precision Calibration P-grade option optimiSes RMS phase jitter performance with a 69 fs (typical) specification for the primary frequencies needed in 56G SerDes designs. The Si5391 is a true sub-100 fs “clock tree on a chip” solution designed to synthesize all output frequencies from the same IC while meeting 56G PAM-4 reference clock jitter requirements with margin.

The Si539x jitter attenuators have been designed to meet the exacting specifications and high-performance requirements of Internet infrastructure, these ultra-low jitter clocks reduce cost and complexity for a wide range of timing applications.

The Si539x can generate any combination of output frequencies from any input frequency while delivering industry-leading jitter performance (90 fs RMS phase jitter). Si5395/4/2 P-grade devices offer best-in-class jitter (69 fs RMS typical phase jitter) for 56G/112G SerDes clocking applications.

The Si56x Ultra Series VCXO and XO family is intended for next-generation high-performance timing applications requiring ultra-low jitter oscillators. Si56x VCXO/XOs are customisable to any frequency up to 3 GHz, supporting twice the operating frequency range of previous Silicon Labs VCXO products with half the jitter. The Si56x oscillators are available with single, dual, quad, and I2C-programmable options in industry-standard 5 mm x 7 mm and 3.2 mm x 5 mm packages, enabling drop-in compatibility with traditional XO, VCXOs and VCSOs. This family features devices with typical phase jitter as low as 90 fs.

Silicon Labs is also offering the Si54x Ultra Series XO family for applications requiring tighter stability and guaranteed long-term reliability, such as optical transport networking (OTN), broadband equipment, data centres and industrial systems.

They are purpose-built for 56G designs, which rely on four-level pulse-amplitude modulation (PAM-4) signalling for serial data transmission to increase the bit rate per channel while keeping the bandwidth constant.

Using an Si54x XO as a low-jitter reference clock maximizes signal-to-noise ratio (SNR) headroom, minimizes bit errors and enhances signal integrity. The Si54x family offers best-in-class performance, with typical phase jitter as low as 80 fs.

Author
Neil Tyler