Through-Silicon Via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSVs are a high performance technique to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package, because the density of the vias is substantially higher, and because the length of the connections is shorter. In TSV wafers or the chips are stacked on top of each other, and are connected using vertical pathways of interconnects (instead of wires) that run completely through the chips. The chips can be of the same type or of different types, referred to as homogeneous or heterogeneous integration, respectively.

Through-Silicon Vias (TSV) Technology for Smart 3D-Package Chip Integration3D IC package (System in Package, Chip Stack MCM, etc.) contains two or more chips (ICs) stacked vertically, the stacked chips are wired together along their edges, this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. A most practical alternate type of 3D package is Through-Silicon Via (TSV) 3D-IC, which was found in IBM’s Silicon Carrier Packaging Technology, where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In the new TSV 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking).

Through-Silicon Via (TSV) is the ultimate 3D interconnect. TSV is emerging as a critical technique for scaling, packaging and continuing the drive to higher density and higher performance ICs. The industry is moving past the feasibility (R&D) phase for TSV technology into the commercialization phase where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated and process equipment and materials are available.

Applications for 3D TSV packages include MEMS sensors, image sensors, flash, DRAM, processors, FPGAs, and power amplifiers. The timing for mass production depends on how the TSV compares in terms of cost with existing technologies.