Q. Expand Verilog?
Q. Implement a full adder using two half adders?
Q. How do you detect if two 8-bit signals are same?
Q. How do you detect a sequence of “1101” arriving serially from a signal line?
Q. How do you differentiate between wires and registers in Verilog ?
Q. How do you diff between blocking vs. non-blocking statements in Verilog ?
Q. Sensitivity lists declaration in always block for sequential and combinational logic?
Q. How to implement tri-state logic in verilog?

Q. Differentiate between tasks and functions in Verilog?
Q. Write a verilog code to swap contents of two registers with and without a temporary register?
Q. What is the difference between blocking and non-blocking assignment statements?
Q. What is the difference between task and function?
Q. Difference between $monitor,$display & $strobe?
Q. What is difference between Verilog full case and parallel case?
Q. What is meant by inferring latches? How to avoid it?
Q. Variable and signal which will be Updated first?
Q. What is sensitivity list?
Q. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if yes, why?
Q. Can you tell me some of system tasks and their purpose?
Q. Write a Verilog code for synchronous and asynchronous reset?
Q. What is PLI? Why is it used?
Q. What is difference between freeze deposit and force?
Q. Will case infer priority register? if yes how give an example?
Q. What is the difference between CASEX and CASEZ? Which is preferable? Why?
Q. What are Intertial and Transport Delays ?
Q. Why is it that “if (2’b01 & 2’b10)…” doesn’t run the true case?
Q. What are Different types of Verilog Simulators ?
Q. What is Constrained-Random Verification ?
Q. Difference between inter statement and intra statement delay?
Q. What is delta simulation time?
Q. Tell me how blocking and non blocking statements get executed?
Q. Tell me structure of Verilog code you follow?
Q. Difference between Verilog and vhdl?
Q. What are different styles of Verilog coding? I mean gate-level,continuous level and others explain in detail?
Q. Can you list out some of enhancements in Verilog 2001?
Q. There is a triangle and on it there are 3 ants one on each corner and are free to move along sides of triangle what is probability that they will collide?
Q. What is the difference between:
c = foo ? a : b;
and
if (foo) c = a;
else c = b;
Q. What are Intertial and Transport Delays ?
Q. What is the difference between === and == ?
Q. How to generate sine wav using verilog coding style?
Q. What is the difference between wire and reg?
Q. How do you implement the bi-directional ports in Verilog HDL?
Q. How to write FSM is verilog?
Q. How can you pass parameters to your simulation?
Q. What are advantages of soft and hard macrofunctions ?
Q. How rnmos, rpmos, rcmos, rtran, rtranif1, and rtranif0 devices reduce the strength of signals that pass through them?
Q. What are different strength in Vreilog and their strength value?
Q. How to declare mos switch (Syntax)?
Q. What are Compiler directives and list some of them?
Q. What are Verilog System tasks and functions , can you list some of them?
Q. What are different options that can be used with $display in Verilog?
Q. What are different operators that verilog supports ?
Q. What is Operator presedence in verilog?
Q. What is default data type of byte, shortint, int, integer and longint?
Q. What is void data type how it can be used ?
Q. What is Casting?
Q. Why we must keep combinational logic together in verilog?
Q. What are unit delays in verilog ? give example?
Q. What Is a Simulation Race in verilog?
Q. What is typical verilog simulator algorithm?
Q. How can we Controlling the dump operation via a command line in verilog?
Q. How to declare memories in Verilog ?
Q. What is difference between <<< and << in verilog?
Q. What are different types of looping statements in verilog?
Q. What is the difference between unary and logical operators?
Q. What is the difference between compiled, interpreted, event based and cycle based simulators?
Q. What is the difference between ( = = , ! = ) and ( = = = , ! = = )?
Q. What is the difference between a = #10 b; and #10 a = b; ?
Q. What does `timescale 1 ns/ 1 ps’ signify in a verilog code?
Q. What is the use of defparam?
Q. Give 10 commonly used Verilog keywords.
Q. Is it possible to optimize a Verilog code such that we can achieve low power design?
Q. Why cannot initial statement be synthesizeable ?
Q. Write code for async reset D-Flip-Flop.
Q. Write code for 2:1 MUX using different coding methods.
Q. Write code for a parallel encoder and a priority encoder.
Q. What is code coverage and what are the different types of code coverage that one does ?
Q. What is file I/O?