Q. Why is it important to keep code for generators/scoreboards and code for BFMs separated?
Q. Which of the parts in the testbench should add data to the scoreboard?
Q. What is the Verification testing?
Q. What is the difference between verification and validation? And what are procedures of doing the same?
Q. What is the difference between the constraints that are added through the test file and those constraints that are placed in the environment files themselves?

Q. What is the difference between testing and verification?
Q. What is the difference between protocol checking and data checking? In which part of the testbench should each be done?
Q. What is the difference between Formal verification and Logic verification?
Q. What is meant by ATPG?
Q. What are the problems you faced when interacting with the client?
Q. What are the multicast routing protocols?
Q. What are the messages in a DHCP messgaes exchanged between the server and the client and which of them are broadcast?
Q. What are the differences between directed testbench and random testbench?
Q. What are the ATM O&M messages?
Q. What are test scenarios (also known as sequences)? What are they used for? Do the use of test scenarios makes the testbench more or less random?
Q. What are stuck-at faults?
Q. What are different types of timing verifications?
Q. Suppose you have a scoreboard for a specific block inside the DUT. Will that scoreboard be useful during end to end (or full chip) tests as well? What for?
Q. What is the difference between declarative code (also known as static (code) and sequential code
Q. Is it a must to have an automatic checker (a scoreboard) in a directed testbench? Is it a must in a random testbench?
Q. How many values can be assigned using the Differentiated Services Code Point (DSCP)?
Q. For f = AB+CD if B is S-a-1 what r the test vectors needed to detect the fault?
Q. For an AND-OR implementation of a two input Mux how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)?
Q. Explain about stuck at fault models scan design.
Q. Draw the structure of a typical random testbench describing each of the parts in detail?
Q. What is the difference between blocking and non- blocking statements?
Q. Describe the entire verification cycle of a particular block testing?
Q. At which phase the use of sequences is more common at the beginning or at the middle?
Q. What is DFT? What is its importance?
Q. Expand BIST? Explain?
Q. What is the difference between testing and verification?
Q. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
Q. What’s the critical path in a SRAM?
Q. Define a test bench?
Q. What are the advantages of test benches?
Q. What is Back annotation?
Q. What is DRC and LVS and name some tools which are used for these operations?
Q. What is Meta stability state?
Q. Explain setup time and hold time in digital circuits.
Q. Explain False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .
Q. Explain Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.
Q. When are DFT and Formal verification used?